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| TECHNICAL DATA IN74AC651 Octal 3-State Bus Transceivers and D Flip-Flops High-Speed Silicon-Gate CMOS The IN74AC651 is identical in pinout to the LS/ALS651, HC/HCT651. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. These devices consists of bus transceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-to-A Source are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The IN74AC651 has inverted outputs. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A, 0.1 A @ 25C * High Noise Immunity Characteristic of CMOS Devices * Outputs Source/Sink 24 mA ORDERING INFORMATION IN74AC651N Plastic IN74AC651DW SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 24=VCC PIN 12 = GND Rev. 00 IN74AC651 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V C C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Rev. 00 IN74AC651 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 Guaranteed Limits 25 C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.6 -40C to 85C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 6.0 A A V Unit V VIL VOUT=0.1 V or VCC-0.1 V V VOH IOUT -50 A V VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT 50 A * VIN=VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA IIN IOZ Maximum Input Leakage Current Maximum ThreeState Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN(OE)=VIH or VIL VIN=VCC or GND VOUT=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND * IOLD IOHD ICC 5.5 5.5 5.5 8.0 75 -75 80 mA mA A * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC Rev. 00 IN74AC651 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol Parameter V Guaranteed Limits 25 C Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ CIN COUT Propagation Delay, A-to-B Clock or B-to-A Clock to A or B Data Port (Figure 1) Propagation Delay, A-to-B Clock or B-to-A Clock to A or B Data Port (Figure 1) Propagation Delay, Input A to Output B or Input B to Output A (Figures 2,3) Propagation Delay, Input A to Output B or Input B to Output A (Figures 2,3) Propagation Delay, A-to-B Source or B-to-A Source to A or B Data Port (Figure 4) Propagation Delay, A-to-B Source or B-to-A Source to A or B Data Port (Figure 4) Propagation Delay, Output Enable to A Data Port (Figure 5) Propagation Delay, Output Enable to A Data Port (Figure 5) Propagation Delay, Output Enable to A Data Port (Figure 5) Propagation Delay, Output Enable to A Data Port (Figure 5) Propagation Delay, Direction to B Data Port (Figure 6) Propagation Delay, Direction to B Data Port (Figure 6) Propagation Delay, Direction to B Data Port (Figure 6) Propagation Delay, Direction to B Data Port (Figure 6) Maximum Input Capacitance Input/Output Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 5.0 4.0 2.5 3.0 2.0 3.0 2.0 2.5 1.5 3.0 2.5 2.5 2.0 2.5 1.5 2.5 1.5 3.0 2.0 2.5 2.0 3.0 2.0 2.5 1.5 3.5 2.5 3.0 2.5 4.5 15 Max 17.0 12.0 14.5 10.5 14.0 9.5 13.0 9.0 14.0 10.0 13.5 10.0 12.0 9.0 12.0 9.0 13.0 11.0 12.5 10.5 12.5 9.5 12.5 9.5 13.5 11.5 13.5 11.5 -40C to 85C Min 3.0 2.0 2.5 1.5 2.5 1.5 2.0 1.0 2.5 2.0 2.0 1.5 2.0 1.0 2.0 1.0 2.5 1.5 2.0 1.5 2.5 1.5 2.0 1.0 3.0 2.0 2.5 2.0 4.5 15 Max 19.0 14.0 16.5 12.0 16.0 11.0 15.0 10.5 16.0 11.5 15.5 11.5 13.5 10.0 14.0 10.5 14.0 12.0 14.0 12.0 14.0 10.5 14.5 11.0 14.5 12.5 15.0 13.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Unit Typical @25C,VCC=5.0 V CPD * Power Dissipation Capacitance 60 pF Voltage Range 3.3 V is 3.3 V 0.3 V Voltage Range 5.0 V is 5.0 V 0.5 V Rev. 00 IN74AC651 TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol tsu th tw Parameter Minimum Setup Time, A or B Data Port to Ato-B Clock or B-to-A Clock (Figure 7) Minimum Hold Time, A-to-B Clock or B-to-A Clock to A or B Data Port (Figure 7) Minimum Pulse Width, A-to-B Clock or B-to-A Clock (Figure 7) V 5.0 5.0 5.0 Guaranteed Limits 25 C 7.0 2.5 6.0 -40C to 85C 8.0 2.5 7.0 Unit ns ns ns TIMING DIAGRAM Rev. 00 IN74AC651 FUNCTION TABLE Dir. L OE H CAB CBA SAB SBA X X X X X X A INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs. The output functions of the A and B bus are disabled. Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. The A bus are outputs and the B bus are inputs. The data at the B bus are displayed at the A bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops, are displayed at the A bus. The data at the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus. OUTPUTS X* L L X* X X X L L H L H L INPUTS L H L H X* X* X X X H H Qn L H X H L INPUTS X H H X* X* L L X X H L H L OUTPUTS The A bus are inputs and the B bus are outputs. L H L H The data at the A bus are displayed at the B bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops are displayed at the B bus. The data at the A bus are stored to the internal flip-flops on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus. The data stored to the internal flip-flops are displayed at the A and B bus respectively. The output at the A bus are displayed at the B bus, the output at the B bus are displayed at the A bus respec. X X* X* H H X X X H L Qn L H OUTPUTS H L X X H H Qn OUTPUTS Both the A bus and the B bus are outputs Qn H H Qn Qn X : DON'T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO TRANSITION OF THE CLOCK INPUTS Rev. 00 IN74AC651 SWITCHING DIAGRAMS Figure 1. Switching Waveforms Figure 2. A Data Port = Input, B Data Port = Output Figure 3. A Data Port = Output, B Data Port = Input Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms Rev. 00 IN74AC651 EXPANDED LOGIC DIAGRAM Rev. 00 IN74AC651 N SUFFIX PLASTIC DIP (MS - 001AF) A Dimension, mm 24 13 B 1 12 Symbol A B C MIN 31.24 6.1 MAX 32.51 7.11 5 .33 F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H J M H J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AD) Dimension, mm A 24 13 Symbol A MIN 15.2 7.4 2.35 0.33 0.4 1.27 9.53 0 0.1 0.23 10 0.25 MAX 15.6 7.6 2.65 0.51 1.27 H B P B C 1 G 12 C R x 45 D F G J F M -TD 0.25 (0.010) M T C M K SEATING PLANE H J K M P R NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 8 0.3 0.32 10.65 0.75 Rev. 00 |
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